This invention relates to the manufacture of integrated circuit devices, and more particularly, to devices, such as dynamic random access memories (DRAMs) that include in a silicon chip both a memory array area where is located an array of memory cells in which information is stored and a support area where is located support circuitry that controls reading and writing of the individual memory cells by way of bit and word lines.
In the manufacture of DRAMs there is a trend towards increasing the number of memory cells in a DRAM and this typically involves decreasing the size of the memory cells in the DRAM and spacing them closer. Moreover, to keep costs low, it is desirable to keep the number of processing steps as small as possible.
A DRAM includes a semiconductive chip, generally of silicon, in which are formed the active circuit elements appropriately interconnected by a pattern of conductive paths (electrical conductors) disposed between dielectric layers. The DRAM typically has one or more memory array areas which contain memory cells and support areas which contain circuitry used to control reading, writing, refreshing, of information in the memory cells as well as other functions such as sensing information read out of the memory cells. For purposes of this application, it will be convenient to view the conductive paths as comprising conductive contact layers at the outer surfaces of appropriate regions of the circuit elements, such as transistor switches and storage capacitors, conductive interconnection lines that are generally horizontal and parallel to the top surface of the wafer, such as the bit and word lines, and conductive vias (electrical conductors, studs) that are generally vertical and interconnect the contact layers to the interconnection lines. In particular, in the method of manufacturing a form of DRAM that the present invention aims to improve, there are three distinct connections of these, the first type is typically described as an electrical contact to bit line (CB) which electrically connects bit lines to drain/source regions of the transistors in the memory array areas. The second type is typically described as a contact to diffusion (CD) that electrically contacts various diffused regions in a semiconductor substrate such as source and drain regions of transistors in the support areas. The third type is typically described as an electrical contact to the gates (CG) and it involves the connection of the word lines to the gates of the transistors both in the array and support areas. Because of the manner in which the interconnections are customarily made, to be described below, the manufacturing process, which this invention seeks to improve is believed to be unnecessarily complex in that it requires more masking steps than desired.
It is desirable to reduce the number of processing steps used to fabricate DRAMs.
The present invention is directed to an integrated circuit, e.g., a DRAM, and a process for fabricating an integrated circuit, e.g., a DRAM, which requires one less masking step than conventional (prior art) processes. The improved processing of the present invention makes it feasible to form electrical contacts to a conductive layer of a gate stack of transistors of a support area of an integrated circuit (silicon chip) in one processing sequence involving the use of only one mask and a single etching and deposition step. This is made possible by use of a masking step that permits use of an etchant that etches the silicon dioxide covering a gate stack and a silicon nitride capping layer that forms a top layer of the gate stack.
Viewed from a first apparatus aspect, the present invention is directed to an integrated circuit formed in and/or on a semiconductor substrate that is covered by first and second dielectric layers and that comprises a plurality of devices formed in and/or on the semiconductor substrate with at least some of the devices having contact regions which are covered by a third dielectric layer which has a different etch characteristic than the first and second dielectric layers. The integrated circuit comprises first, second and third continuous electrical conductors. The first continuous electrical conductor extends through the first, second, and third dielectric layers and makes electrical contact to a contact region of one device. The second continuous electrical conductor extends through the first dielectric layer and makes electrical contact to a contact region of a device which does not have a third dielectric layer covering the contacted contact region. The third continuous electrical conductor extends through the second dielectric layer and makes electrical contact to the second continuous electrical conductor.
Viewed from a second apparatus aspect, the present invention is directed to a dynamic random access memory that is formed in a silicon chip that is covered by first and second dielectric layers and that comprises a memory array area that includes an array of memory cells each comprising a field effect transistor which each include source and drain regions and a gate stack, formed over a channel region and spaced therefrom by a gate dielectric, that includes in turn a doped-polysilicon conductive gate, a metal contact layer, a dielectric capping layer, and a dielectric spacer along sidewalls thereof that include silicon nitride, and a support area that includes field effect transistors which each include source and drain regions and a gate stack, formed over a channel region portion of the silicon chip and spaced therefrom by a gate dielectric, that includes in turn a doped-polysilicon conductive gate, a metal contact layer, a dielectric capping layer, and a dielectric spacer along sidewalls thereof that include silicon nitride. The the dynamic random access memory comprises a plurality of first second and third continuous electrical conductors. The plurality of first continuous electrical conductors extends through the first and second dielectric layers with at least one of said first continuous conductors extending through the capping dielectric layer of the gate stack of one support transistor to the metal contact layer of the gate stack. The plurality of second continuous electrical conductors extends through the first dielectric layer with at least one of said continuous electrical conductors contacting the drain region of a transistor of a memory cell of the memory area and at least two other of the second continuous electrical conductors with one contacting the drain region and one contacting the source region of one support transistor of the support area. The plurality of third continuous electrical conductors extends through the second dielectric layer with one of the third continuous electrical conductors electrically contacting one of the plurality of second continuous electrical conductors which contacts the drain region of a transistor of a memory cell, and with a second of the third continuous conductors electrically contacting the one of the second continuous electrical conductors which electrically contacts the drain region of the transistor of a support transistor of the support area, and with a third of the second continuous electrical conductors electrically contacting the one of the second continuous electrical conductors which electrically contacts the source region of the support transistor of the support area.
Viewed from a first process aspect, the present invention is directed to a method for forming an integrated circuit in a semiconductor substrate. The method comprises the steps of: forming in and/or on the semiconductor substrate devices which have contact regions with at least one of the devices having a contact region which is covered by a first dielectric layer; covering the surface of the substrate with a second dielectric layer that is planarized and that covers the devices, the second dielectric layer having a different etch characteristic than the first dielectric layer; patterning the second planarized dielectric layer to provide openings therethrough to contact regions of devices that are not covered by the first dielectric layer; filling the openings in the second planarized layer of dielectric with conductive material to form electrical contacts to the contact regions of devices that are not covered by the first dielectric layer; covering the second dielectric layer with a third planarized dielectric layer, the third dielectric layer having a different etch characteristic than the first dielectric layer; patterning the third planarized dielectric layer to form openings therethrough and through the second dielectric layer and the first dielectric layer to contact regions of the devices which are covered by the first dielectric layer; and filling openings in the first, second, and third dielectric layers with conductive material to provide electrical conductors to the contact regions which have the first dielectric layer covering same and to provide electrical conductors to the electrical conductors previously formed through the second dielectric layer to contact contact regions not covered by the first dielectric layer.
Viewed from a second process aspect, the present invention is directed to a method for forming in a silicon chip a dynamic random access memory that includes an array of memory cells in an array area of the chip and support circuitry in a support area of the chip. The method comprises the steps of: forming in the array area of the chip an array of memory cells including array transistors and in the support area support circuitry including support field effect transistors, each of the transistors including source and drain regions and a gate stack overlying a channel region at the surface of the chip separating a source region and a drain region thereof; covering the surface of the chip with a first planarized layer of a dielectric that encloses the gate stacks of the array and the support transistors; patterning the first planarized layer of dielectric to provide openings therethrough to the drain regions of the transistors in the array area and to the source and drain regions of the transistors of the support area; filling the openings in the first planarized layer of dielectric with conductive material to form electrical contacts to the drain regions of the transistors in the array area and to the source and drain regions of the transistors in the support areas; covering the previously covered silicon chip with a second planarized layer of dielectric; patterning the second planarized layer of dielectric to form openings therethrough and through the first dielectric layer to the gates of the gate stacks of the transistors in the support area and through the second dielectric layer to the electrical contacts to the drain regions of the transistors in the array area and through the first dielectric layer to the electrical contacts of the source and drain regions of the transistors in support areas; and filling openings in the first and second dielectric layers with a conductor to provide electrical conductors to the gates of the support transistors, and filling the openings in the second dielectric layer to provide electrical conductors to the electrical conductors previously formed through the first dielectric layer to the drain regions of the array transistors and to the sources and drain regions of the support transistors.
Viewed from a third process aspect, the present invention is directed to a method for use in the fabricating a semiconductor chip housing a dynamic random access memory (DRAM) having memory cells each comprising a field effect transistor having source and drain regions and a gate, and support circuitry comprising field effect transistors each having a source and drain regions and a gate, for forming electrical connections through formed first and second dielectric layers covering the chip to drain regions of field effect transistors of memory cells and to drain and source regions and gates of at least one of the field effect transistors of the support circuitry of the DRAM. The method comprises the steps of: before the second dielectric layer is formed over the chip, defining and etching first openings through the first dielectric layer to the drain regions of the transistors of the memory cells and to the source and drain regions of at least one of the transistors of the support circuitry; filling the first openings in the first dielectric layer with conductive material and then forming the second dielectric layer over the chip, said conductive material forming electric contacts to the drain regions of the transistors of the memory cells and to the drain and source regions of at least one of the transistors of the support circuitry; defining and etching first openings through the second dielectric layer which terminate at the conductive material previously used to fill the first openings in the first dielectric layer, and defining and etching additional first openings through the second dielectric layer which also extend through the first dielectric layer to form second opening through the first dielectric layer which extend to the gates of the support transistors; filling all the first openings in the second dielectric layer and the second openings in the first dielectric layer with conductive material such electrical contacts through the first and second dielectric layers are made to the drains of the transistors of the memory cells and to the source and drain regions and gate of transistors of the support circuitry.
The invention will be better understood from the following more detailed description in conjunction with the accompanying drawing.